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Master's Dissertation
DOI
10.11606/D.3.2014.tde-12122014-153226
Document
Author
Full name
Ricardo Cardoso Rangel
E-mail
Institute/School/College
Knowledge Area
Date of Defense
Published
São Paulo, 2014
Supervisor
Committee
Martino, João Antonio (President)
Diniz, José Alexandre
Onmori, Roberto Koji
Title in Portuguese
Sequência simples de fabricação de transistores SOI nMOSFET.
Keywords in Portuguese
Educação (Microeletrônica)
Microeletrônica
MOSFET
SOI
Transistores
Abstract in Portuguese
Neste trabalho é desenvolvido de forma inédita no Brasil um processo simples de fabricação de transistores FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) com porta de silício policristalino, para servir como base para futuros desenvolvimentos e, também, com finalidade de educação em microeletrônica. É proposta uma sequência de etapas de fabricação necessárias para a obtenção do dispositivo FD SOI nMOSFET, usando apenas 3 etapas de fotogravação e usando o óxido enterrado, intrínseco à tecnologia SOI, como região de campo, objetivando a obtenção do processo mais simples possível e eficiente. São apresentados os procedimentos detalhados de todas as etapas de fabricação executadas. Para obtenção da tensão de limiar de 1V foram fabricadas amostras com 2 doses diferentes de implantação iônica, 1,0x1013cm-2 e 1,2x1013cm-2. Estas doses resultaram em tensões de limiar (VTH) de 0,72V e 1,08V; respectivamente. Como esperado, a mobilidade independente de campo (0) é maior na amostra com dose menor, sendo de 620cm²/Vs e, para a dose maior, 460cm²/Vs. A inclinação de sublimiar é calculada através da obtenção experimental do fator de acoplamento capacitivo () 0,22; para as duas doses, e resulta em 73mV/déc. O ganho intrínseco de tensão (AV) mostrou-se maior na amostra com maior dose em função da menor condutância de saída, sendo 28dB contra 26dB para a dose menor, no transistor com L=40m e W=12m. Desta forma foi possível implementar uma sequência simples de fabricação de transistores SOI, com resultados elétricos relevantes e com apenas 3 etapas de fotogravação, fato importante para viabilizar seu uso em formação de recursos humanos para microeletrônica.
Title in English
Simple sequence of manufacture of transistors SOI nMOSFET.
Keywords in English
Education (Microelectronics)
Microelectronics
MOSFET
SOI
Transistors
Abstract in English
In this work is developed in an unprecedented way in Brazil a simple process of manufacturing transistors FD SOI nMOSFET (Fully-Depleted Silicon-On-Insulator) with gate polysilicon, to serve as the basis for future developments and also with the purpose of education in microelectronics. A sequence of manufacturing steps necessary for obtaining FD SOI nMOSFET device is proposed, using only three photolithographic steps and using the buried oxide, intrinsic to SOI technology such as field region, aiming to get the simplest possible and efficient process. All the detailed manufacturing steps performed procedures are presented. To obtain the threshold voltage of 1V samples with 2 different doses of ion implantation (1.0x1013cm-2 and 1.2 x1013cm-2) were fabricated. These doses resulted in threshold voltages (VTH) of 0.72 V and 1.08 V, respectively. As expected, mobility independent of field (0) is higher in the sample with the lowest dose, 620cm²/Vs, and for the higher dose, 460cm²/Vs. The subthreshold slope is calculated by obtaining experimental capacitive coupling factor () 0.22, for both doses and results in 73mV/déc. The intrinsic voltage gain (AV) was higher in the sample with a higher dose due to lower output conductance, 28dB against 26dB to the lowest dose, to the transistor with L = W = 40m and 12m. This made it possible to implement a simple sequence of manufacturing SOI transistors with relevant electrical results and with only 3 steps photolithographic important fact to enable their use in training human resources for microelectronics.
 
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Publishing Date
2015-01-15
 
WARNING: The material described below relates to works resulting from this thesis or dissertation. The contents of these works are the author's responsibility.
  • RANGEL, R., et al. 3D Transistor (FinFET) Fabricated with Three Lithography. In SEMINATEC 2013 - VIII Workshop on Semiconductors and Micro & Nano Technology, Campinas, 2013. Proceedings of SEMINATEC 2013 - VIII Workshop on Semiconductors and Micro & Nano Technology., 2013.
  • RANGEL, R., et al. Fully Electron-Beam-Lithography SOI FinFET. In 28th Symposium on Microelectronics Technology and Devices - SBMicro 2013, Curitiba, 2013. Proceedings of SBMicro 2013. : IEEE, 2013.
  • RANGEL, R., CARRENO, M., and MARTINO, J. A. Microelectronics Education: Design, Fabrication and Characterization of Self-Aligned Silicon-Gate nMOSFET Technology. In VII Workshop on Semiconductors and Micro & Nano Technology - SEMINATEC 2012, São Bernardo do Campo, 2012. Proceedings of the VII Workshop on Semiconductors and Micro & Nano Technology.São Bernardo do Campo : Centro Universitário da FEI, 2012.
All rights of the thesis/dissertation are from the authors
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